C06-18: Iddq Trending as a Precursor to CMOS IC Failure
Objective:
Demonstrate a low current sensor to monitor the in-circuit trend in Iddq of a CMOS IC. The current data will be digitized and fed to a trend detection algorithm. The prognostic value lies in the detection of an increase in slope.
Background:
Iddq testing has been in use for many years by semiconductor manufacturers as a method of detecting early life die related failures. This technique can discover die-level failure mechanisms such as gate oxide shorts or breakdown. This technique has potential in electronics prognostics as an upswing in Iddq is indicative of imminent failure.
Decreasing semiconductor feature sizes (90nm and below) and the corresponding increasing gate density are causing Iddq levels to increase, thus making it more difficult to set absolute detection thresholds. Use of change detection sidesteps this difficulty.
Approach:
1st Year
- An accelerated high temperature operating life (HTOL) test using a selection of representative CMOS ICs will be conducted and Iddq measured. The test conditions will be derived from the qualification test processes of the IC suppliers. The ICs will be instrumented using standard laboratory equipment to monitor Iddq. This test will obtain the current v. time characteristics and identify the dynamic range and resolution requirements for the sensor. This test will also show typical spectrum and noise characteristics to enable a signal processing scheme to be developed.
- Potential low current sensing techniques will be researched and a selection made. The objective is to find a low cost sensing technique that can be constructed as a stand-alone device to be added to any circuit.
2nd Year
- Construct a prototype sensor and test (HTOL) with a set of representative CMOS ICs.
- Construct and test a data collection and signal analysis scheme to measure, digitize, reduce, filter and trend the sensor output.